RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

riscv.org

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China bets on open-source chips as US export controls mount (www.reuters.com)
submitted 6 months ago by [email protected] to c/[email protected]
1 comments fedilink
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Vectorizing Unicode conversions on real RISC-V hardware (camel-cdr.github.io)
submitted 7 months ago by [email protected] to c/[email protected]
1 comments fedilink
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Edge AI chiplet uses SemiDynamics RISC-V cores (www.eenewseurope.com)
submitted 7 months ago by [email protected] to c/[email protected]
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China Is All In on a RISC-V Future (www.hpcwire.com)
submitted 7 months ago by [email protected] to c/[email protected]
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CEO interview: MIPS’ Sameer Wasson on a RISC-V reboot (www.eenewseurope.com)
submitted 7 months ago by [email protected] to c/[email protected]
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MIPS snags top SiFive brains to amp up RISC-V business – Drew Barbier and Brad Burgess join after restructure at former employer (www.theregister.com)
submitted 7 months ago by [email protected] to c/[email protected]
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First RISC-V mini laptops emerge (www.notebookcheck.net)
submitted 8 months ago by [email protected] to c/[email protected]
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RISC V 101 - talks from RISC-V Summit (farside.link)
submitted 8 months ago by [email protected] to c/[email protected]
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This CPU is FREE! - Invidious (inv.tux.pizza)
submitted 8 months ago by possiblylinux127 to c/[email protected]
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This CPU is FREE! - LTT video about Milk-V (farside.link)
submitted 8 months ago* (last edited 8 months ago) by [email protected] to c/[email protected]
0 comments fedilink
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Meta Sees Little Risk in RISC-V Custom Accelerators (www.nextplatform.com)
submitted 8 months ago by [email protected] to c/[email protected]
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RISC-V Summit: Ghosts of x86 and ARM Linger (www.hpcwire.com)
submitted 9 months ago by [email protected] to c/[email protected]
0 comments fedilink
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Why Nordic is getting involved in RISC-V (blog.nordicsemi.com)
submitted 9 months ago by [email protected] to c/[email protected]
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Ventana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo | Tom's Hardware (www.tomshardware.com)
submitted 9 months ago by [email protected] to c/[email protected]
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China Deploys Massive RISC-V Server in Commercial Cloud (www.hpcwire.com)
submitted 9 months ago by [email protected] to c/[email protected]
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Synopsys joins RISC-V party with fresh embedded core designs (www.theregister.com)
submitted 9 months ago by [email protected] to c/[email protected]
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RISC-V summit in Santa Clara. Schedule: (events.linuxfoundation.org)
submitted 9 months ago by [email protected] to c/[email protected]
0 comments fedilink
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Regarding Proposed US Restrictions on RISC-V - a letter to Joe Biden (www.bunniestudios.com)
submitted 9 months ago by [email protected] to c/[email protected]
1 comments fedilink
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SiFive at the Ubuntu summit in Riga: (www.youtube.com)
submitted 9 months ago by [email protected] to c/[email protected]
2 comments fedilink
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AMD MicroBlaze V Processor: A Flexible and Efficient RISC-V Processor (www.xilinx.com)
submitted 9 months ago by [email protected] to c/[email protected]
5 comments fedilink
 
 

The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD adaptive SoCs and FPGAs. The MicroBlaze V processor is based on a 32-bit RISC-V instruction set architecture (ISA). It allows developers to leverage the open-source RISC-V software ecosystem, is hardware compatible with the classic MicroBlaze processor, and is fully integrated in the Vivado™ and Vitis™ tools design flow. The MicroBlaze V processor is designed to be highly modular with a configurable architecture suitable for embedded systems applications.

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AMD MicroBlaze V (www.ept.ca)
submitted 9 months ago by [email protected] to c/[email protected]
0 comments fedilink
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BeagleV®-FireRISC-V, FPGA and open hardware, all together now (www.beagleboard.org)
submitted 9 months ago by [email protected] to c/[email protected]
2 comments fedilink
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RISC-V & US politics cont. (www.firstpost.com)
submitted 9 months ago by [email protected] to c/[email protected]
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US politicians really don't seem to be able to grasp the idea of Open Standards, do they? :/

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RISC-V + CHERI (www.electronicsweekly.com)
submitted 9 months ago by [email protected] to c/[email protected]
3 comments fedilink
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Android and RISC-V: What you need to know to be ready (opensource.googleblog.com)
submitted 9 months ago by [email protected] to c/[email protected]
0 comments fedilink
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