RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

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Box64 and RISC-V in 2024 - What It Takes to Run The Witcher 3 on RiSC-V (box86.org)

submitted 2 months ago by [email protected] to c/[email protected]

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[–] [email protected] 2 points 2 months ago* (last edited 2 months ago)

There appears to be dedicated silicon for e.g. ADD AH, BL, see uops.info showing it having 1 uop across multiple microarchitectures (e.g. 1*p0156 being notation that it takes one uop on any port between 0/1/5/6, i.e. theoretical throughput of 4 instrs/cycle; I think the displayed 0.4 is just an artifact of it only testing 3 different destination registers despite there being a dependency on it). The newer Alder Lake actually has less throughput, but still takes only one uop.