I guess just making sure my understanding aligns - RISC V being the instruction set, and you are wondering if anyone is building a CPU to implement it?
Came across a couple examples, if that’s what you mean
Hardware
https://www.sifive.com/technology/risc-v
Cloud
https://www.nextplatform.com/2023/02/02/the-first-risc-v-shot-across-the-datacenter-bow/